Abstract & Overview
Quantum-dot Cellular Automata is an evolving post-CMOS paradigm that can be used for designing nanoscale circuits. Digital circuits are implemented in QCA using majority logic. Adder and subtractor are used widely in almost every data processing system. For efficient hardware implementation, a single hardware can be used to perform both addition as well as subtraction. In this paper, a novel majority logic-based adder-subtractor architecture is proposed. The proposed architecture is implemented in QCA and validated using the coherence vector simulation engine in QCADesigner tool. The results show that the proposed design has fewer cell count, area and latency compared to the existing designs. During fabrication, QCA circuits can face manufacturing defects. A detailed fault analysis is made for the proposed design for different manufacturing defects. Parameters to calculate the fault tolerant ability of QCA circuits are introduced and calculated for the proposed design.